1. Field of the Invention
The present invention relates to memory cell devices, and more particularly to a non-volatile memory cell device and method which provides for improved self-converged programming of multiple bit levels.
2. Description of Related Art
Non-volatile memory cells are used to store bits of information which comprise digital words and the like. Such memory cells include floating gate transistor devices which have a drain, source, and gate nodes. The gate includes a control gate for application of a voltage, and a floating gate which floats in a layer of material between the device substrate and control gate. Voltages are applied across the nodes in such a way as to induce current flow through the device and cause hot electrons to jump over to the floating gate. The bits of information are therefore stored as a charge or voltage level on the floating gate of the cell, and the charge will remain until the cell is erased or reprogrammed. In the past, memory cells have commonly been used to store two levels of information, e.g. high for "1" or "on," and low for "0" or "off." These on and off states are arranged in collected memory cells to comprise binary strings of information which are used by computers and digital processing devices.
Memory cells have also been used to store multiple levels of data on an individual cell. Instead of two states (on or off), a series of levels can be programmed into the memory cell and then read back as multiple states. For instance three levels will provide four data bits for a single cell (e.g. zero plus three distinct voltage levels). Accordingly, this will provide higher storage densities for a given number (or array) of memory cells. Multi-level programming of devices such as flash EEPROMs (electronically erasable programmable read only memories) will allow for increased storage capacity without increasing the die size used to form the overall device. The end result is a reduced cost per bit.
For realizing multi-level programming, accurate control of the amount of charge placed on the floating gate of a memory cell is important. Many different programming methods have been previously proposed to control the amount of charged stored on the floating gate, such as program-and-verify and self-convergence methods. The program-and-verify method is widely used and involves programming the memory cell in a ramped or step-wise fashion via a programming pulse. After each programming step is applied, a verification step is performed to confirm whether the desired level on the memory cell has been achieved. Problems inherent with this method include slow programming speed, as each programming and verification step takes a certain amount of time to perform. In addition, a very stable pulse control is necessary to prevent overshoot of each programming level. Examples of modern program-and-verify methods include: M. Bauer et al., "A Multilevel-Cell 32 Mb Flash Memory," IEEE ISSCC Digest of Technical Papers, pp. 132-133, 1995; and Y. Choi et al., "A High Speed Programming Scheme For Multi-Level NAND Flash Memory," Symp. on VLSI Circuits Digest of Technical Papers, pp. 170-171, 1996.
Accordingly, self-convergence methods provide advantages regarding programming speed and pulse control requirements. In general, the memory cell is programmed by connecting the drain node to a dataline, the gate node to certain voltage, and the source node to a current source or ground (hence the line is also referred to as a source line). Note also that drain side sensing configurations can also be used. When a memory cell is programmed to a higher target threshold voltage (Vt), the voltage at the current source (Vs) will become proportionally lower to keep relatively the same programming current through the memory cell. Thus, Vt and Vs of the memory cell have a one-to-one correlation. By monitoring Vs, the corresponding Vt can be achieved through this correlation. One method employing this effect is described in U.S. Pat. No. 5,712,815 (see FIG. 1 in detailed description). Three reference voltages are used to define memory cells with four different levels. The current source voltage Vs is compared to the desired reference voltage Vref, and when Vs drops below Vref, then the programming will stop automatically. An array of reference memory cells is also provided which are programmable to different reference levels. It has been found that for read operations, a voltage margin is needed above the target voltage level to compensate for possible drops that might occur as a result of the read. The differently programmed reference cells provide this read margin.
Improved memory cell devices and programming methods are required, however, to achieve a tighter distribution of read current and programming levels in light of such detrimental things including loading effects, process variations, temperature variations, and supply voltage variations. A tighter distribution will provide the benefit of even more levels being made available for multiple bits from a single cell.